Abstract—This paper discusses the design of an IC layout for 7-segment counter. The layout was designed by using Electric VLSI Design System as Electronic Design Automation (EDA) tool. In order to produce the layout, the fabrication process of Integrated Circuit (IC) was further explored to ensure the layout could be successfully drawn. The complete layout of the counter was designed based on the schematic circuit which consists of a few JK flip-flops. The layout had undergone Design Rule Check (DRC) set by the Electric VLSI Design System to check for any design rule error. Both layout and schematic circuit of the counter were then simulated through Layout versus Schematic (LVS) to ensure they were identical. The simulation outputs of the counter indicated that result of the layout and schematic circuit were not ideal due to noises occurred in JK flipflops.

Index Terms—7-segments counter, schematic circuit, IC layout, electric VLSI design system, DRC, LVS, simulation output

Cite: Teen Soh Hong and Lee Sin Yin, "Cmos Ic Layout Design: 7- Segments Counter," Lecture Notes on Photonics and Optoelectronics, Vol. 1, No. 2, pp. 52-55, December 2013. doi: 10.12720/lnpo.1.2.52-55