Abstract—This paper describes the design of a low power, high sampling rate track-and-hold amplifier (THA) which can be used in pipeline analog-to-digital converter (ADC). The THA can samples at 100 MS/s and only dissipates 12mW under 3V power supply. The amplifier is a fully differential two stage amplifier without miller compensation for power consumption reduction while maintaining enough gain and bandwidth. It is fabricated in 0.35um CMOS process and integrated in a 8-bit 100MS/s pipeline ADC. The THA makes the ADC achieve nearly 60dBc spur-free dynamic range(SFDR) and 58.1 total harmonic distortion (THD) at supply voltage of 3V in under sampling mode and can be used in medium resolution and high speed under sampling pipeline ADC.

Index Terms—THA; CMOS; SFDR; THD; pipeline

Cite: Xiaodan Zhou, Ai Guo, and Chen Su, "A Low Power High Linearity THA for 8Bit 100Msample/s Pipeline ADC," Lecture Notes on Photonics and Optoelectronics, Vol. 1, No. 2, pp. 44-47, December 2013. doi: 10.12720/lnpo.1.2.44-47